Peter Kogge, University of Notre Dame
Thomas Sterling, California Institute of Technology & Jet Propulsion Laboratory, Vice Chair

Charter:

Identify opportunities and challenges for innovative HEC system architectures, including alternative execution models, support mechanisms, local element and system structures, and system engineering factors to accelerate rate of sustained performance gain (time to solution), performance to cost, programmability, and robustness. Establish a roadmap of advanced-concept alternative architectures likely to deliver dramatic improvements to user applications through the end of the decade. Specify those critical developments achievable through custom design necessary to realize their potential.

Guidelines and Questions:

• Present driver requirements and opportunities for innovative architectures demanding custom design
• Identify key research opportunities in advanced concepts for HEC architecture
• Determine research and development challenges to promising HEC architecture strategies. Project brief roadmap of potential developments and impact through the end of the decade.
• Specify impact and requirements of future architectures on system software and programming environments.
• Example Topics:
  • System-on-a-chip (SOC), Processor-in-memory (PIM), streaming, vectors, multithreading, smart networks, execution models, efficiency factors, resource management, memory consistency, synchronization

Slides presented during Plenary Reports on Findings (134 KB PDF)

<< Back to Road Map Workshop home page

<< Back to the Road Map Workshop Agenda